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DS1249W
3.3V 2048kb Nonvolatile SRAM
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FEATURES
10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation Read and write access times as fast as 100ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Optional industrial (IND) temperature range of -40C to +85C JEDEC standard 32-pin DIP package
PIN ASSIGNMENT
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
32-Pin Encapsulated Package 740mil Extended
PIN DESCRIPTION
A0-A17 DQ0-DQ7
CE WE OE
VCC GND NC
- Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+3.3V) - Ground - No Connect
DESCRIPTION
The DS1249W 2048kb nonvolatile (NV) SRAMs are 2,097,152-bit, fully static, NV SRAMs organized as 262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing.
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103102
DS1249W
READ MODE
The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs (A0 - A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than tACC.
WRITE MODE
The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge.
DATA-RETENTION MODE
The DS1249W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8V. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protects themselves, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.5V, the power-switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 3.0V.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation.
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DS1249W
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * -0.3V to +4.6V 0C to 70C (-40C to +85C for IND parts) -40C to +70C (-40C to +85C for IND parts) +260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power-Supply Voltage Logic 1 Logic 0 SYMBOL VCC VIH VIL MIN 3.0 2.2 0.0 TYP 3.3 MAX 3.6 VCC +0.4
(TA: See Note 10)
UNITS V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current CE VIH VCC Output Current at 2.2V Output Current at 0.4V Standby Current CE = 2.2V Standby Current CE = VCC - 0.2V Operating Current Write Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VTP
(TA: See Note 10; VCC = 3.3V 0.3V)
MIN -2.0 -2.0 -1.0 2.0 150 100 2.8 2.9 250 150 50 3.0 TYP MAX +2.0 +2.0 UNITS mA mA mA mA mA mA mA V NOTES
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 10 10 MAX 20 20
(TA = +25C)
UNITS pF pF NOTES
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DS1249W
AC ELECTRICAL CHARACTERISTICS
PARAMETER Read Cycle Time Access Time
OE CE OE
(TA: See Note 10; VCC = 3.3V 0.3V)
DS1249W-100 DS1249W-150
SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
MIN 100
MAX 100 50 100
MIN 150
MAX 150 70 150
UNITS ns ns ns ns ns
NOTES
to Output Valid to Output Valid or CE to Output Active
5 35 5 100 75 0 5 20 35 5 40 0 20
5 35 5 150 100 0 5 20 35 5 60 0 20
5 5
Output High-Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time
ns ns ns ns ns ns ns ns ns ns ns ns
3 12 13 5 5 4 12 13
READ CYCLE
SEE NOTE 1
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DS1249W
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
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DS1249W
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER VCC Fail Detect to CE and WE Inactive VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to CE and WE Inactive VCC Valid to End of Write Protection SYMBOL tPD tF tR tPU tREC 150 150 2 125 MIN TYP MAX 1.5
(TA: See Note 10)
UNITS ms ms ms ms ms NOTES 11
(TA = +25C)
PARAMETER Expected Data-Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition in Write Cycle 1, the output buffers remain in a high-impedance state during this period.
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DS1249W
7. If the CE high transition occurs prior to, or simultaneously with, the WE high transition, the output buffers remain in a high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to, or simultaneously with, the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1249W has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to +70C. For industrial products (IND), this range is -40C to +85C. 11. In a power-down condition, the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. DS1249 modules are recognized by Underwriters Laboratory (U.L.a) under file E99151.
DC TEST CONDITIONS
Outputs open Cycle = 200ns for operating current All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0 to 2.7V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1249W - SSS - III Operating Temperature Range blank: 0C to +70C IND: -40C to +85C Access Speed 100: 100ns 150: 150ns
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DS1249W
DS1249W NONVOLATILE SRAM, 32-PIN, 740MIL EXTENDED MODULE
PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 32-PIN MIN 2.080 52.83 0.715 18.16 0.395 10.03 0.280 7.11 0.015 0.38 0.120 3.05 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.43 MAX 2.100 53.34 0.740 18.80 0.405 10.29 0.310 7.49 0.030 0.76 0.160 4.06 0.110 2.79 0.630 16.00 0.012 0.30 0.025 0.58
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